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ATC
4096-bits Serial Electrically Erasable PROM Features
* State-of-the-art architecture - Non-volatile data storage - Standard voltage and low voltage operation Vcc: 2.7V ~ 5.5V - Full TTL compatible inputs and outputs - Auto increment read for efficient data dump * Hardware and software write protection - Defaults to write-disabled state at power up - Software instructions for write-enable/disable - VCC level verification before self-timed programming cycle * Advanced low voltage CMOS EEPROM technology * Versatile, easy-to-use interface - Self-timed programming cycle - Automatic erase-before-write - Programming status indicator - Word and chip erasable - Stop SK anytime for power savings * Durability and reliability - 40 years data retention - Minimum of 1M write cycles per word - Unlimited read cycles - ESD protection
AM93LC66
General Description
The AM93LC66 is the 4096-bit non-volatile serial EEPROM. It is manufactured by using ATC's advanced CMOS EEPROM technology. The AM93LC66 provides efficient non-volatile read/write memory arranged as 256 words of 16 bits each when the ORG Pin is connected to VCC and 512 words of 8 bits each when it is tied to ground. The instruction set includes read, write, and write enable/disable functions. The data out pin (DO) indicates the status of the device during the self-timed non-volatile programming cycle. The self-timed write cycle includes an automatic erase-before-write capability. Only when the chip is in the WRITE ENABLE state and proper VCC operation range is the WRITE instruction accepted and thus to protect against inadvertent writes. Data is written in 16 bits per write instruction into the selected register. If Chip Select (CS) is brought HIGH after initiation of the write cycle, the Data Output (DO) pin will indicate the READY/BUSY status of the chip. The AM93LC66 is available in space-saving 8-lead PDIP, 8-lead SOP and rotated 8-lead SOP package.
Connection Diagram
Pin Assignments
Name CS SK DI DO GND VCC NC ORG Description Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply No Connection Internal Organization
CS SK DI DO
1 2 3 4
8 7 6 5
VCC NC ORG GND
NC VCC CS SK
1 2 3 4
8 7 6 5
ORG GND DO DI
PDIP-8L / SOP-8L
Rotated SOP-8L
Ordering Information
AM 93 L C 66 X XX X
Operating Voltage LC : 2.7~5.5V,CMOS
Type 66: 4K
Temp. grade o o Blank : 0 C ~ +70 C o o I : - 40 C ~ +85 C V : - 40 o C ~ +125 o C
Package S : SOP-8L GS : SOP-8L,G type N : PDIP-8L
Packing Blank : Tube A : Taping
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Rev.A1 Oct 20, 2003 1/10
ATC
4096-bits Serial Electrically Erasable PROM Block Diagrams
DI
INSTRUCTION REGISTER (11 BITS) DATA REGISTER DUMMY BIT
AM93LC66
DO
R/W AMPS
CS
INSTRUCTION DECODE CONTROL AND CLOCK GENERATION
ADDRESS REGISTER
DECODER EEPROM ARRAY (256 X 16) OR (512 X 8)
VCC RANGE DETECTOR
SK
WRITE ENABLE HIGH VOLTAGE GENERATOR
ORG
Absolute Maximum Ratings
Characteristics Storage Temperature Voltage with Respect to Ground Symbol TS Values -65 to + 125 -0.3 to + 6.5 Unit C V
NOTE:These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
Operating Conditions
Temperature under bias AM93LC66 AM93LC66I AM93LC66V Values 0 to + 70 -40 to + 85 -40 to +125 Unit C C C
DC Electrical Characteristics
Parameter Operating current** Standby current Input leakage Output leakage Input low voltage** Input high voltage** Output low voltage Output high voltage Output low voltage Output high voltage Symbol ICC ISB IIL IOL VIL VIH VOL1 VOH1 VOL2
(Vcc =2.7~5.5V, Ta = 25oC , unless otherwise noted) Min Max Units 3 mA 10 A 1 A 1 A 0.15 VCC V 0.8 VCC +0.2 V VCC+0.2 0.4 V V 0.2 V V
Conditions CS=VIH, SK=1MHz CMOS input levels CS=DI=SK=0V VIN = 0V to VCC(CS,SK,DI) VOUT = 0V to VCC, CS=0V VCC = 3V + 10% VCC = 5V + 10% VCC = 3V + 10% VCC = 5V + 10% IOL = 2.1mA TTL, VCC=5V + 10% IOH = -400uA TTL, VCC=5V + 10% IOL = 10uA CMOS IOH = -10uA CMOS
-1 -1 -0.1 -0.1 0.8 VCC 2 2.4 VCC -0.2
Note **: ICC , VIL min and VIH max are for reference only and are not tested
Anachip Corp. www.anachip.com.tw 2/10
Rev. A1 Oct 20, 2003
ATC
4096-bits Serial Electrically Erasable PROM
AM93LC66
AM93LC66 Min Max 0 1 250 250 250 50 100 0 100 500 500 500 100 10 1M
AC Electrical Characteristics (Vcc = 2.7V ~ 5.5V, Ta = 25oC , unless otherwise noted)
Parameter SK Clock Frequency SK High Time SK Low Time Minimum CS Low Time CS Setup Time DI Setup Time CS Hold Time DI Hold Time Output Delay to "1" Output Delay to "0" CS to Status Valid CS to DO in 3-state Write Cycle Time 5V, 25C, Page Mode Symbol FSK TSKH TSKL TCS TCSS TDIS TcSH TDIH TpD1 TpD0 TSV TdF TwP Endurance** Conditions Units MHz ns ns ns ns ns ns ns ns ns ns ns ms write cycles
Relative to SK Relative to SK Relative to SK Relative to SK AC Test AC Test AC Test CL = 100pF CS = VIL
Note** : The parameter is characterized and isn't 100% tested.
1.247V
(1 TTL Gate Load)
632 ohm DO 100PF
FIGURE 1. AC TEST CONDITIONS
Instruction Set
Instruction READ WEN (Write Enable) WRITE WRALL (Write All Registers) WDS (Write Disable) ERASE ERAL (Erase All Registers) Start Bit 1 1 1 1 1 1 1 OP Code 10 00 01 00 00 11 00 Address x8 x 16 A 8 - A0 A7 - A0 11 XXXXXXX 11XXXXXX A8 - A0 A7 - A0 01XXXXXXX 01XXXXXX 00 XXXXXXX 00XXXXXX A 8 - A0 A7 - A0 10 XXXXXXX 10XXXXXX Input Data x8 x 16
D7 - D0 D7 - D0
D15 - D0 D15 - D0
Anachip Corp. www.anachip.com.tw 3/10
Rev. A1 Oct 20, 2003
ATC
4096-bits Serial Electrically Erasable PROM Pin Capacitance ** (Ta=25C , f=1MHz )
Symbol COUT CIN Parameter Output capacitance Input capacitance Max 5 5 Units pF pF
AM93LC66
Note ** :The parameter is characterized and isn't 100% tested.
Functional Descriptions
Applications The AM93LC66 is ideal for high volume applications requiring low power and low density storage. This device uses a low cost, space saving 8-pin package. Typical applications include robotics, alarm devices, electronic locks, meters and instrumentation settings such as LAN cards, monitors and MODEM. Endurance and Data Retention The AM93LC66 is designed for applications requiring up to 1M programming cycles (WRITE, WRALL, EARSE and ERALL). It provides 40 years of secure data retention. Device Operation The AM93LC66 is controlled by seven 11-bit instructions. Instructions are clocked in (serially) on the DI pin. Each instruction begins with a logical "1" (the start bit). This is followed by the opcode (2 bits), the address field (8 bits), and data, if appropriate. The clock signal (SK) may be halted at any time and the AM93LC66 will remain in its last state. This allows full static flexibility and maximum power conservation. Read (READ) The READ instruction is the only instruction that outputs serial data on the DO pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a 8-bit or 16-bit serial shift register. (Please note that one logical "0" bit precedes the actual 8-bit or 16-bit output data string.) The output on DO changes during the rising edge transitions of SK. (Shown in Figure 3) Auto Increment Read Operations Sequential read is possible, since the AM93LC66 has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 8-bit or 16-bit of the
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addressed word have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS high until the chip select (CS) control pin is brought low. This allows for single instruction data dumps to be executed with a minimum of firmware overhead. Write Enable (WEN) Before any device programming (WRITE, WRALL, ERASE, and ERAL) can be done, the WRITE ENABLE (WEN) instruction must be executed first. When Vcc is applied, this device powers up in the WRITE DISABLE state. The device then remains in a WRITE DISABLE state until a WEN instruction is executed. Thereafter the device remains enabled until a WDS instruction is executed or until Vcc is removed. (NOTE: Neither the WEN nor the WDS instruction has any effect on the READ instruction.) (Shown in Figure 4) Write Disable (WDS) The WRITE DISABLE (WDS) instruction disables all programming capabilities. This protects the entire part against accidental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the WRITE DISABLE state.) To protect data, a WDS instruction should be executed upon completion of each programming operation. (NOTE: Neither the WEN nor the WDS instruction has any effect on the READ instruction.) (Shown in Figure 5)
Rev. A1 Oct 20, 2003
ATC
4096-bits Serial Electrically Erasable PROM Functional Descriptions (Continued)
Write (WRITE) The WRITE instruction includes 8-bit or 16-bit of data to be written into the specified register. After the last data bit has been applied to DI, and before the next rising edge of SK, CS must be brought LOW. The falling edge of CS initiates the self-timed programming cycle. After a minimum wait of 250ns (5V operation) from the falling edge of CS (tcs), DO will indicate the READY/BUSY status of the chip if CS is brought HIGH. This means that logical "0" implies the programming is still in progress while logical "1" indicates the selected register has been written, and the part is ready for another instruction. (See Figure 6) Note: The combination of CS HIGH, DI HIGH and the rising edge of the SK clock, resets the READY/BUSY flag. Therefore, it is important if you want to access the READY/BUSY flag, not to reset it through this combination of control signals. Before a WRITE instruction can be executed, the device must be in the WRITE ENABLE (WEN) state. Write All (WRALL) The Write All (WRALL) instruction programs all registers with the data pattern specified in the instruction. While the WRALL instruction is being loaded, the address field becomes a sequence of DON'T-CARE bits. (Shown in Figure 7) As with the WRITE instruction, if CS is brought HIGH after a minimum wait of 250ns (tcs), the DO pin indicates the READY/BUSY status of the chip. (Shown in Figure 7) Erase (ERASE) After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after minimum of tcs, will cause DO to indicate the READ/BUSY status of the chip. To explain this, a logical "0" indicates the programming is still in progress while a logical "1" indicates the erase cycle is complete and the part is ready for another instruction. (Shown in Figure 8) Erase All (ERALL) Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical "1". (Shown in Figure 9) Security Consideration To protect the entire part against accidental modification of data, each programming instruction (WRITE, WRALL, ERASE, and ERALL) must satisfy two conditions before user initiate self-timed programming cycle (the falling edge of CS). One is that the AM93LC66 is at WEN status. The other is that the VCC value must exceed a lock-out value which can be adjusted by ANALOG TECHNOLOGY INC.
AM93LC66
Anachip Corp. www.anachip.com.tw 5/10
Rev. A1 Oct 20, 2003
ATC
4096-bits Serial Electrically Erasable PROM Timing Diagram (1)
AM93LC66
T CS tCSS SK tDIS DI tDIH tSKH tSKL tCSH
DO(READ)
tPDO
tPD1
tDF
tSV DO(WRITE) (WRALL) (ERASE) (ERALL) STATUS VALID
tDF
FIGURE 2. SYNCHRONOUS DATA TIMING
tCS CS + SK 0
DI
TRI-STATE
1
1
AN
AO
DO
*
O DN DO
+For all instructions, SK cycles before start bit don't care. *Address Pointer Cycle to the Next Register.
FIGURE 3. DATA READ CYCLE TIMING
Anachip Corp. www.anachip.com.tw 6/10
Rev. A1 Oct 20, 2003
ATC
4096-bits Serial Electrically Erasable PROM Timing Diagram (2)
AM93LC66
tCS CS SK ** DI 1 DO = TRI-STATE **AN-2 ~A0 don't care. 0 0 1 1 X- - - - - - - - - - - X
FIGURE 4. WRITE ENABLE(WEN) CYCLE TIMING
tCS CS
SK ** X- - - - -- - - - X
DI
1
0
0
0
0
DO = TRI-STATE **AN-2 ~A0 don't care.
FIGURE 5. WRITE DISABLE(WDS) CYCLE TIMING
tCS CS
SK
DI
TRI-STATE
1
0
1
AN
AO
DN
DO
tSV DO
BUSY READY
tDF
tWP
FIGURE 6. WRITE(WRITE) CYCLE TIMING
Anachip Corp. www.anachip.com.tw 7/10
Rev. A1 Oct 20, 2003
ATC
4096-bits Serial Electrically Erasable PROM Timing Diagrams (3)
tCS CS
AM93LC66
SK
**
DI
1
0
0
0
1
X- - - - - - - - - - - -X
DN
DO
tSV DO
TRI-STATE BUSY READY
**AN-2~A0 don't care.
tWP
FIGURE 7. WRITE ALL(WRALL) CYCLE TIMING
tCS CS
SK
AN AO
DI
1
1
1
tSV
TRI-STATE BUSY READY
tDF
DO
tWP
FIGURE 8. ERASE(ERASE) CYCLE TIMING
tCS CS
SK 1 0 0 1 0 ** X- - - - - - - - - X tSV DO
TRI-STATE BUSY READY
DI
tDF
**AN-2~A0 don't care.
tWP
FIGURE 9. ERASE ALL(ERALL) CYCLE TIMING
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Rev. A1 Oct 20, 2003
ATC
4096-bits Serial Electrically Erasable PROM Package Diagrams
(1) Plastic Dual-in-line Package: PDIP-8L
AM93LC66
D
E-PIN O0.118 inch
E1
E 15 (4X) PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
7 (4X) eB A2 A
C
L
B S e B1 B2
Symbol A A1 A2 B B1 B2 C D E E1 e L eB S
Dimensions in millimeters Min. Nom. Max. 5.33 0.38 3.1 3.30 3.5 0.36 0.46 0.56 1.4 1.52 1.65 0.81 0.99 1.14 0.20 0.25 0.36 9.02 9.27 9.53 7.62 7.94 8.26 6.15 6.35 6.55 2.54 2.92 3.3 3.81 8.38 8.89 9.40 0.71 0.84 0.97
A1
Dimensions in inches Min. Nom. Max. 0.210 0.015 0.122 0.130 0.138 0.014 0.018 0.022 0.055 0.060 0.065 0.032 0.039 0.045 0.008 0.010 0.014 0.355 0.365 0.375 0.300 0.313 0.325 0.242 0.250 0.258 0.100 0.115 0.130 0.150 0.330 0.350 0.370 0.028 0.033 0.038
Anachip Corp. www.anachip.com.tw 9/10
Rev. A1 Oct 20, 2003
ATC
4096-bits Serial Electrically Erasable PROM
(2) JEDEC Small Outline Package: SOP-8L
AM93LC66
E
H
L VIEW "A" D 7 (4X) A2 A
0.015x45
7 (4X)
A1
e
B y
C
VIEW "A"
Symbol A A1 A2 B C D E e H L y
Dimensions In Millimeters Min. Nom. Max. 1.40 1.60 1.75 0.10 0.25 1.30 1.45 1.50 0.33 0.41 0.51 0.19 0.20 0.25 4.80 5.05 5.30 3.70 3.90 4.10 1.27 5.79 5.99 6.20 0.38 0.71 1.27 0.10 8O 0O
Dimensions In Inches Min. Nom. Max. 0.055 0.063 0.069 0.040 0.100 0.051 0.057 0.059 0.013 0.016 0.020 0.0075 0.008 0.010 0.189 0.199 0.209 0.146 0.154 0.161 0.050 0.228 0.236 0.244 0.015 0.028 0.050 0.004 0O 8O
Marking Information
Top view
Part Number (X:ID Code) Blank : PDIP-8L & SOP-8L (Commercial) I : PDIP-8L & SOP-8L (Industrial) V : PDIP-8L & SOP-8L (Automotive) G : Rotated SOP-8L (Commercial) B : Rotated SOP-8L (Industrial) D : Rotated SOP-8L (Automotive)
Anachip Corp. www.anachip.com.tw 10/10
ATC 93LC66X YYWW X
Logo Date & ID Code YY : Year WW : Week X: Internal
Rev. A1 Oct 20, 2003

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